CPU Simulator

Step through the Fetch-Decode-Execute cycle

FETCH

DECODE

EXECUTE

Central Processing Unit

PC 0

MAR -

MDR -

CIR -

ACC 0

Control Unit (CU)

ALU

[A] Address
➔

[D] Data
➔ ⬅

[C] Control
➔ ⬅

Main Memory

Addr	Data

Ready. Click 'Next Micro-Step' to begin the Fetch-Decode-Execute cycle.

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See exactly what happens inside a CPU. Step through the Fetch-Decode-Execute cycle one micro-operation at a time — watch registers update, buses carry data, and memory respond at every stage.

Covers AQA, OCR, and EDUQAS specifications.

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